1. Field of the Invention
The invention relates in general to a substrate and a manufacturing method of a package structure, and more particularly to a substrate with a solder mask exposing part of a cutting area and a manufacturing method of a package structure.
2. Description of the Related Art
As technology develops, all kinds of new electronic products enabling people to handle things more easy. The electronic products perform digital calculation through chips with micro-electric circuits, for providing all kinds of electric functions. The chip is disposed on a substrate and electrically connected to the substrate through wire-bonding or flip-chip bonding. Inner circuits of the chip are electrically connected to an outer circuit through the substrate. Furthermore, the chip and the substrate are encapsulated by a sealant to form a package structure. The sealant can protect the chip form moisture or collision.
However, in the manufacturing process of the package structure, generally the substrate is a multiple substrate for increasing the manufacturing speed. Several chips are disposed on the multiple substrate. After the chips are packaged by a series of steps, the multiple substrate is cut to form several package structures. As a result, the manufacturing speed increases significantly.
Please refer to FIGS. 1A˜1B at the same time. FIG. 1A illustrates a first surface 900a of a conventional substrate 900. FIG. 1B illustrates a second surface 900b of the conventional substrate 900. The substrate 900 includes the first surface 900a, the second surface 900b, a die-attaching area 980, a cutting area L900 and a groove 990. The die-attaching area 980 is located on the first surface 900a for attaching a die (not shown in FIGS. 1A˜1B). The groove 990 penetrating the first surface 900a and the second surface 900b is formed on the cutting area L900. As shown in FIG. 1A and FIG. 1B, the cutting area L900 is a dotted rectangular loop. Four grooves 990 are formed on four sides of the cutting area L900. After the chips are packaged, four corners of the cutting area L900 are cut by using a cuter to form several rectangular package structures.
As shown in FIG. 1A, the substrate 900 further includes a first solder mask 910. The solder mask 910 covers the first surface 900a for protecting inner circuits of the substrate 900. The first solder mask 910 covers the entire first surface 900a and only exposes several first pads 930. The first pads 930 are for electrically connecting the chips. What is worth mentioning is that the first solder mask 910 totally covers the four corners of the cutting area L900.
As shown in FIG. 1B, the substrate 900 further includes a second solder mask 920. The second solder mask 920 cover the second surface 900b for protecting the inner circuits of the substrate 900. The second solder mask 920 covers the entire second surface 900b and exposes only several second pads 940. The second pads 940 are for electrically connecting to an outer circuit. What is worth mentioning is that the second solder mask 920 totally covers the four corners of the cutting area L900
However, the thermal expansion coefficients of the inner circuit, the first solder mask 910 and the second solder mask 920 do not match each other. As a result, the first solder mask 910 and the second solder mask 920 often crack. In general, the cracks often extend form the edges of the first solder mask 910 or the second solder mask 920 to central regions. When the cracks extend to the first solder mask 910 or the second solder mask 920 inside the cutting area L900, the strength of the package structure is affected seriously.
Furthermore, when the cutter cut the substrate 900 along the cutting area L900, the first solder mask 910 and the second solder mask 920 directly contact the cutter and are under the stress of the cutter. As a result, the first solder mask 910 or the second solder mask 920 peels off due to the stress.
As stated above, when the first solder mask 910 or the second solder mask 920 cracks or peels off, the package structure cannot protect the chip effectively. The yield rate of the package structure is significantly lowered, and the manufacturing cost is increased. Therefore, it is very important to resolve the above problems.